1. Field of the Invention
The present invention relates generally to the field of integrated circuit design, and, more specifically, to power routing in ASIC design.
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2. Background Art
Designers of integrated circuit chips, such as application specific integrated circuits (xe2x80x9cASIC xe2x80x9d), typically rely on a computer aided design (xe2x80x9cCAD xe2x80x9d) program using a hardware description language to assist in their design. Hardware description languages allow the designer to specify, in software, the logical operation of the chip they are designing. Typical hardware description languages include Verilog, Synopsys MCL (module compiler language), and Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL).
Present design processes consist of several steps. First, the designer writes a description of a circuit in the form of a software program describing the flow of signals in the chip and the logical operations performed on those signals. In Verilog, for example, such a program is written at the so-called xe2x80x9cRegister Transfer Level xe2x80x9d (xe2x80x9cRTL xe2x80x9d). Once the designer has programmed the operation of the logic circuit, the program is simulated and, if acceptable, synthesized into a corresponding collection of standard cells. Standard cells are components, such as logic gates, latches, decoders, and various other components, that exist in a library accessible by a synthesis tool. The synthesis step is typically an automated process in which the synthesis tool determines the appropriate standard cells and interconnections between standard cells to realize a circuit that satisfies the RTL model. At this point, the chip is ready for physical design; that is, the physical placement of the synthesized standard cells and the routing of interconnections (wires) among them. Physical designers typically use automated tools to aid in placement and routing. Once the physical design is complete, process masks are obtained from the generated layout, and those process masks are used in the chip foundry to process the desired integrated circuit from semiconductor materials (e.g., silicon wafers).
Power routing is an important step in the physical design phase of ASIC design. Traditionally, power routing is performed during the floor planning stage, before cell placement. The separation between power routing and cell placement limits the designer""s ability to control the power routing according to the cell placement. This is because the locations of the standard cells, and hence the power consumption behavior of the circuit, are not yet known at the power routing stage. This power routing flow also creates obstacles for cell placement optimization, which result in poor placement and lower area utilization (e.g., fewer gates per unit area). Since an accurate power analysis is not possible during the floor planning stage, a conservative power planning strategy must be taken. This conservative strategy also results in lower silicon utilization.
Prior to placing standard cells in a physical layout, power routing operations set up a power ring and power straps, for example, in the vicinity of where standard cells will be placed. A power ring is a power bus that bounds a physical area, whereas a power strap is a power bus that spans a power ring. The power ring and power straps represent obstacles to the placement of standard cells, leading to non-optimized cell placement in many cases. Also, when the power ring and power straps are initially placed in the physical layout, general assumptions are made about how power will be consumed in the circuit. These assumptions may or may not accurately reflect actual power consumption patterns of the placed standard cells. For process technologies above one micron, the power assumptions may prove satisfactory. However, with technology advances in submicron processing regimes leading to smaller, more densely packed circuits, inaccuracies in power distribution have greater negative impact on circuit performance. Further, as low-power designs increase in popularity, efficient power distribution becomes more of an issue in circuit design. By performing power routing before placement of standard cells, current systems are prevented from providing optimized power distribution with reference to actual power use patterns of the final circuit layout.
A method and apparatus for performing power routing in ASIC design are described. Power routing is performed after cell placement, allowing more knowledgeable placement of power structures in the physical layout. By performing cell placement prior to power routing, standard cells are allowed to be placed in more optimal configurations. In one embodiment, power rings and power straps are placed over the top of the standard cells based on power analysis of the standard cell layout. Those regions of the layout where design violations are triggered are corrected by an incremental placement correction of affected cells. In another embodiment, cells are placed in the physical layout in a bottom-up hierarchical manner. When a given cell becomes large enough to require power routing, a power feed cell of sufficient dimension to support the necessary power strap is inserted into the circuit layout during the placement process. In the subsequent power routing phase, power straps are placed over the power feed cells.